Integrated circuits (ICs) and, more specifically, application specific integrated circuits (ASICs) are becoming more and more complex, and are operating at ever increasing clock speeds. Accordingly, testing the functionality of integrated circuits is becoming an ever increasing challenge for IC test designers and engineers. Generally, testing an integrated circuit falls into two broad categories, functional testing and structural testing. Functional testing involves stimulating the primary inputs of the integrated circuit and measuring the results at the primary outputs of the integrated circuit. Functional testing exercises the functionality of logic elements within the integrated circuit and is a traditional method to ensure that the integrated circuit can perform its intended operations. However, developing and implementing a high-quality functional test for a complex integrated circuit is very labor intensive, and the application of such a functional test requires costly equipment.
Therefore, to reduce the effort and expense required to test an integrated circuit, structural testing has emerged as an alternative to functional testing. In a structural test, the internal storage elements of the IC are used to control and observe the internal logic. This is generally done by linking the storage elements into a serial shift register when a test mode signal is applied. This technique is referred to as “scan testing”. Scan testing is divided into two broad categories, static scan testing (also referred to as DC scan testing) and dynamic scan testing (also referred to as AC scan testing or scan-based delay testing). Generally, scan testing involves providing a scan chain comprising a number of interconnected multiplexers and registers connected to the combinational logic of the integrated circuit. The registers in the scan chain are typically implemented using D flip-flops. The scan chain can be many hundreds of thousands of flip-flops in length, and is generally divided into a smaller number of shorter parallel scan chains, each comprising approximately one hundred to one thousand flip-flops and multiplexers. The actual number depends on the complexity of the logic to be tested.
During DC scan testing, scan data may be clocked into the scan chain at a clock rate significantly slower than the anticipated operating clock rate of the integrated circuit. After the scan data is loaded into the scan chain registers, a primary input state is applied to the combinational logic of the integrated circuit. The combination of the scanned-in present state and the applied primary inputs comprises the test stimulus. The values of the primary outputs are then measured and a single clock cycle (sometimes referred to as a “clock pulse”) is executed to capture the response of the circuit to the stimulus. To complete the DC scan test, the values captured in the flip-flops are scanned out of the scan chain. As these values are scanned out of the scan chain they are compared to the expected data by test equipment to verify the correctness of the combinational logic within the IC. Unfortunately, DC scan testing allows timing-related faults to remain undetected due to the static nature of the test.
Dynamic (AC) scan testing is similar to DC scan testing with the main difference being the execution of two successive clock pulses at the operating frequency of the integrated circuit being tested during the capture period. By executing two successive clock pulses, the first of which launches transitions and the second of which captures the response of the circuit to these transitions, the timing performance of the circuit can be evaluated.
FIG. 1A is a block diagram illustrating a simplified prior art integrated circuit 10. The integrated circuit 10 includes logic 14 and a scan chain 15 formed through the flip-flops 16. The logic 14 comprises the logic elements that determine the operational parameters of the IC 10. Primary inputs 11 are input to the logic 14 while the primary outputs 12 are obtained based on the response of the logic 14 to the present state of the flip-flops 16 and the values of the primary inputs 11. The integrated circuit 10 also includes a scan chain 15 formed by a plurality of flip-flops 16 preceded by a corresponding plurality of multiplexers (not shown in FIG. 1A), in which the present state output (Q) of a flip-flop is input to both the logic 14 and the next flip-flop in the scan chain 15.
FIG. 1B is a block diagram illustrating in further detail the integrated circuit 10 of FIG. 1A. The integrated circuit 10 includes a plurality of D flip-flops, each preceded by a corresponding multiplexer to facilitate the connection of the scan chain. This type of scan implementation is referred to as “mux-d scan” and is intended to be illustrative and not limiting. In this example, a pad 18, which is referred to as a “scan-in” (SI) pad, supplies scan input data via connection 48 to a first multiplexer 24. The first multiplexer 24 is responsive to a scan enable signal from pad 22. The scan enable (SE) signal 22 is applied to multiplexers 24, 26 and 27. A clock (CK) signal from pad 21 is applied to flip-flops 31, 32, and 33. When the scan enable signal is high (a logic 1) the scan-in input on connection 48 is selected by multiplexer 24 and applied to the D input to the flip-flop 31. Conversely, when the scan enable signal is low (a logic 0), the next state of the flip-flop 31 is provided by the logic 14 via connection 44. The normal operation input to each of the multiplexers 24, 26, and 27 comes from the combinational logic 14 and is selected when the scan enable (SE) signal 22 is low (a logic 0). The output of the flip-flop 33 is supplied via connection 49 to a scan output pad 19. Further, the Q outputs of each flip-flop 31, 32 and 33, are supplied via connections 37, 41 and 49, respectively, as the present state to the logic 14.
Activating the scan enable signal on pad 22 forms a scan chain 15 from flip-flops 31, 32, and 33 by configuring them into a shift register. When scanning in data, successive clock pulses applied via the clock input pad 21 load each of the flip-flops 31, 32 and 33 with a known state. As each new pattern is shifted into the scan chain 15, the old pattern shifts out and is observed, thus testing the response of the IC.
To describe the operation of the scan chain 15 shown in FIG. 1B used in AC scan mode, in a first step, the scan enable signal is set to logic high and data is scanned into each of the flip-flops in the scan chain 15 on a series of successive clock cycles. The clock cycles used to scan in the data to the scan chain may be at a frequency significantly slower than the normal operating frequency of the IC 10. The primary inputs are then loaded and the primary outputs are analyzed. The scan enable signal is then lowered, and, after a brief pause, two successive clock pulses at the normal operating frequency of the integrated circuit 10 are applied to the circuit. This type of AC scan test is referred to as a “broadside” or “system clock launch” test. Other AC scan test protocols such as “last shift launch” or “skewed load” may alternatively be used during this launch/capture portion of the test. A “last shift launched” or “skewed load” scan test uses a last shift of a scan chain to launch a transition, and then applies a single clock pulse to capture the data. After the launch and capture events are complete, the scan enable signal is raised and the data is scanned out of the scan chain 15 via the pad 19 and the scan out data is analyzed. This will be described in greater detail below with respect to FIG. 1C.
FIG. 1C is a timing diagram 50 illustrating the operation of the prior art integrated circuit 10 of FIG. 1B during AC scan testing. The timing diagram 50 is divided into a scan-in period 61, a launch/capture period 62 and a scan-out period 64. The timing diagram 50 also includes a clock (CK) trace 52, a scan enable (SE) trace 54, and primary input (PI) trace 56, a primary output (PO) trace 57, a scan in (SI) trace 58, and a scan out (SO) trace 59. As shown, the clock trace 52 illustrates a series of successive clock cycles that are generated during a scan in period 61, whereby the clock pulses 52 are generated at a frequency (rate) that is significantly slower than the normal operating frequency of the integrated circuit 10 being tested. During the scan in period 61, the scan enable trace 54 indicates that the scan enable signal is at a constant logic high. During the scan-in period 61, the primary inputs generally remain constant, while the primary outputs may transition between logic low and logic high at a frequency determined by the frequency of the clock input 52. Significantly, during the scan-in period 61, the scan-in trace 58 indicates that data is being scanned-in to the registers (flip-flops) within the scan chain 15 at the rate of the clock 52. Though the scan out pad 19 (FIG. 1B) will be active during the scan-in period 61, the scan-out trace 59 indicates that no measured data transitions occur at the scan-out pad 19 during the scan-in period 61 (i.e. the scan out data on pad 19 is ignored during the scan-in period in this example).
During the launch/capture period 62, the scan enable signal 54 transitions from a logic high to a logic low. The primary input trace 56 is then transitioned, thereby loading a desired value into the logic 14, which can occur before, during, or after the transition of the scan enable signal 54. In response, the primary output trace 57 transitions immediately after the primary input trace, giving rise to a period 66 during which the primary outputs can be measured for the timeliness of the response. This portion of the test identifies if there are any delay defects on paths between primary inputs and primary outputs. Though usually affecting only a small portion of most ICs, these delay defects are important because they affect what are often critical speed paths within the IC. A critical speed path in the IC represents the longest propagation time for a data signal traversing the logic contained within the clock domain defined by a particular clock distribution network in the IC.
At a later time within the launch/capture period 62, a pair of clock pulses 65 are provided at the normal operating frequency of the integrated circuit 10 that is being tested. The first clock pulse 67 can be referred to as the “launch” clock pulse and the second clock pulse 68 can be referred to as the “capture” clock pulse. The two successive clock pulses at the normal operating frequency of the integrated circuit allow functional testing of the logic 14 connected between the flip-flops 15 of the integrated circuit. The logic 14 generally represents a majority of the circuitry on the IC 10. A plurality of such patterns comprising scan-in, launch/capture, and scan-out periods is generally required to fully test an IC. Unfortunately, as will be described below with respect to FIG. 2, the two successive clock pulses 65 occurring at the operating frequency of the integrated circuit 10 may be subject to a delay sufficient to cause an erroneous test result to appear. Briefly, the delay is attributed to the voltage drop that occurs on the IC power supply as the launch clock pulse 67 causes switching activity in the logic 14, with the result that the current available to drive the following capture clock pulse 68 is significantly less than what is desired. This voltage drop and resulting current starvation may delay the rise of the capture clock pulse 68 to a point such that the actual test frequency is less than the operating frequency of the integrated circuit 10, thus rendering the AC scan test inaccurate and unreliable.
The scan-out period 64 indicates that the scan enable signal 54 is again at a logic high, thus enabling the scan data to be scanned out of the scan chain 15 via pad 19 at a rate equal to the clock rate 52, which, during the scan out-period 64, is at a rate slower than the normal operating frequency of the IC 10 and similar to the scan-in clock rate.
FIG. 2 is a graphical illustration depicting the effect of voltage drop on the successive clock pulses described in FIG. 1C. The graphical illustration 70 includes an input reference clock (REF_CLK) trace 71, a clock output (CLK—312_OUT) trace 72 and a power supply voltage monitor (VDD_MONITOR) trace 74. The pair of clock pulses 76 shown in clock trace 71 are similar to the launch clock pulse 67 and the capture clock pulse 68 of FIG. 1C. For illustration purposes only, the desired reference clock frequency of the clock pulses 76 is 312.5 megahertz (MHz), which equates to a clock cycle time of 3.2 nanoseconds (ns) for each clock pulse. The clock output trace 72 is responsive to the reference clock input trace 71 and is shown using trace 78. Trace 78 represents the response of the on-chip clock distribution network to the input reference clock pulses, and thus includes a first pulse 79 and a second pulse 80, both of which reflect the insertion delay relative to the reference clock pulses that caused them. The first pulse 79 results from the first pulse 75 of the reference clock 71 and the second pulse 80 results from the second reference clock pulse 77. However, the second clock pulse 80 has an additional delay beyond that due to insertion delay. As shown, the original reference clock period of 3.2 ns has elongated to 3.7 ns after the pulses propagate through the clock distribution network on the integrated circuit 10 (FIG. 1A).
The power supply voltage monitor trace 74 includes a curve 81, which illustrates the clock period elongation described above. The curve 81 begins at a voltage level of 1.8 volts (V) and, upon the initiation of the clock pulse 79, indicates that the voltage begins to drop from 1.8 V down to approximately 1.54 V during the second clock pulse 80. The degradation of the supply voltage (i.e., the voltage drop) from about 1.8 V to about 1.54 V renders the IC incapable of providing adequate current to drive the second rising clock edge in a timely fashion and thus gives rise to the clock period elongation, whereby the clock period beginning at the rising edge of pulse 79 to the rising edge of pulse 80 has been elongated to 3.7 ns. Remember that the input clock frequency of 312.5 MHz corresponds to a clock period of 3.2 ns. The 3.7 ns clock period of the output clock 72 corresponds to approximately 270 MHz clock frequency. Therefore, the voltage drop, as shown by the voltage trace 81, turns a 312.5 MHz input clock into a 270 MHz output clock. This causes the testing of the integrated circuit device 10 to occur at a frequency significantly below the desired frequency.
Therefore, it will be desirable to have a way to measure the amount of clock period elongation caused by voltage drop during testing of an integrated circuit.